As semiconductor technologies become more complex, there is a demand for providing semiconductor structures that have more functionality associated therewith. For example, in order to provide customers with the optimum designs, it may be required to build high performance complementary metal oxide semiconductor (CMOS) devices as well as to add additional functions such as dynamic random access memory (DRAM) or radio frequency (RF) applications. All of the devices are optimized under different conditions. For example, RF and DRAM applications have traditionally been built on bulk semiconductor substrates, while higher performance CMOS devices are typically built on silicon-on-insulator (SOI) substrates.
In CMOS devices built on SOI for instance, performance characteristics are known to be greatly improved. Specifically, CMOS devices built on SOI can exhibit less junction capacitance and leakage, greater resistance to ionizing radiation, and immunity to latch up.
In order to achieve optimum performance however, it would be desirable to provide a substrate that has SOI like properties in some regions of the substrate, while having non-SOI like, i.e., bulk, properties in other regions of the substrate.
A semiconductor substrate having a bulk region and an SOI region has the advantages of excellent crystallization of the bulk region and excellent element insulation of the SOI region. For example, logic memory circuits are preferably formed in bulk element regions while high performance logic circuits are preferably formed in the SOI region. It is desirable, therefore, for a semiconductor device to have areas of SOI and bulk silicon adjacent on the same semiconductor substrate.
Numerous techniques have been developed to form SOI and bulk regions. One of the most manufacturable techniques is ion implantation which involves the implantation of high energy ions into a solid surface to form a buried layer. Because the implanted dopants are generally not in the proper lattice position and are mostly inactive, a high temperature annealing process is often used to repair crystal damage and electrically activate the dopants. Implantation of oxygen into silicon is generally a preferred process for building SOI substrates. The separation by implanted oxygen (SIMOX) process can be used, for example, in very large scale integration (VLSI) devices.
Unfortunately, masked or patterned ion implantation produces a region of partial implantation, referred to as the transition region, in the semiconductor substrate. The transition region forms between the area that receives the full ion implant dose and the region that was shielded from implantation, known as the mask region. As a result of this partial dose, the transition region is highly defective, containing crystal defects that may propagate to other regions of the semiconductor silicon layer.
U.S. Pat. No. 5,740,099 issued to Tanigawa teaches building areas of SOI and bulk silicon wafers on a substrate and building different types of circuits in each area. Tanigawa discusses the concept of making multiple regions of SOI and bulk, on the same wafer, using a patterned ion implant. This method is known to cause defects at all of the patterned edge regions.
U.S. Pat. No. 5,612,246 issued to Ahn describes a method and structure in which standard SIMOX SOI wafers are patterned and then the silicon and buried oxide are etched down to the bulk silicon substrate. Ahn then builds devices on the bulk silicon substrate. One problem with this method is that the structure is non-planar and, therefore, the levels or heights of the bulk and SOI devices are different on the wafer. Consequently, every film that is deposited and etched will leave a sidewall or rail around the step between the two levels of silicon.
U.S. Pat. No. 5,364,800 and U.S. Pat. No. 5,548,149, both issued to Joyner, teach a technique using masking oxide of various thickness to produce a buried oxide layer of differing depths. At the extreme ends of the ranges of the mask thickness, Joyner can create thick SOI, thin SOI, or bulk silicon regions. Thus, Joyner can create a substrate with both SOI and bulk regions.
U.S. Pat. No. 4,889,829 issued to Kawai describes a method of making bulk and SOI regions on the same substrate. Kawai builds the bulk in the original substrate and then deposits, using chemical vapor deposition or CVD, an oxide on top to form the buried oxide. Silicon (polysilicon) is then deposited on top of the oxide. Because high-quality devices cannot be built on polysilicon, Kawai then recrystallizes the poly with a laser to form a single crystal. SOI devices are then built on this layer. The final structure is non-planar, as is the structure taught by Ahn, with the inherent problems of such a structure. In addition, the process described by Kawai is impractical because control over recrystallization of the poly is poor.
U.S. Pat. No. 5,143,862 issued to Moslehi teaches SOI wafer fabrication by selective epitaxial growth. Moslehi etches wide trenches, deposits a buried oxide by CVD, removes the oxide from the sidewalls of the trench, then uses selective epitaxial growth to grow the silicon over the oxide region. Moslehi then isolates the region by forming sidewalls on the epitaxial mask, continues to grow the silicon to the surface, and, finally, removes the sidewalls and etches a trench filled with dielectric to isolate devices.
U.S. Pat. No. 5,399,507 issued to Sun also describes a method and structure for forming bulk and SOI regions on a single substrate. The method starts with blanket SOI (formed by SIMOX) and then etches away the silicon and buried substrate layer down to the silicon substrate. At this step of the method, the structure is similar to the structure disclosed by Ahn in that the structure has an exposed bulk silicon region at a different level than the top of the SOI region. Sun goes further, however, and places a sidewall on the etched opening then uses selective epitaxial growth on the silicon which is a continuation of the single crystal silicon. The epitaxial growth continues up to the surface of the SOI region so that the region is planar. Sun may also use a planarizing step to ensure that the two regions are on the same plane. Sun fails either to improve the patterned implants or to remove any defect regions which may exist.
U.S. Pat. No. 6,255,145 to Ajmera, et al. provides a process for forming a planar SOI substrate comprising a patterned SOI region and a bulk region, in which the substrate is free of transitional defects. The process disclosed in Ajmera, et al. comprises removing the transitional defects by creating a self-aligned trench adjacent the SOI region between the SOI region and the bulk region.
U.S. Pat. No. 6,724,046 to Oyamatsu discloses yet another method of forming a substrate that has SOI like and bulk like regions. This prior art method includes the steps of forming a first insulation film, a first semiconductor layer, and a second insulation film in sequence in first to third regions of a semiconductor substrate; removing the first insulation film, the first semiconductor layer, and the second insulation film in the first region and the second insulation film in the third region; selectively forming a second semiconductor layer in the first region of the semiconductor substrate and on the first semiconductor layer in the third region; and removing the second insulation film.
In view of the state of the art mentioned above, there is still a need for providing a simple method that can be used for forming a semiconductor substrate that has SOI like regions and bulk like regions. Also, there is a need for providing a method of forming a dual depth SOI substrate.